The present invention relates to a chip-like electronic component suitable for use in the manufacture of a semiconductor device and a method of manufacturing the same, and in particular, it relates to a pseudo wafer for use in the manufacture of the same and a method therefor.
Recently, in line with a recent growing demand for a more compact and lightweight design of electronic devices typically represented by a portable information terminal and the like, a very high density packaging technology for packaging semiconductor LSIs (large-scaled integration) in a limited space is attracting much attention.
Conventional high density packaging technology has been challenging how to improve a surface packaging density mainly, and there have been many discussions on a more compact package design, chip scale packaging (CSP), a real chip size CSP using a flip chip connection, and a bare chip packaging technology. Although it is a key point of the discussion at the same time to realize minimization of a gap between respective CSPs or bare chips in the high density packaging, nevertheless how many bare chips are packaged on a surface with a gap therebetween minimized infinitely, a packaging area thereof on a substrate cannot exceed 100%.
By way of example, as a typical bump forming technique in the above-mentioned flip chip packaging method, there are a method for forming Au bumps on an Al electrode pad by using the Au-stud bump process or the electroplating process, and a method for forming solder bumps in batch by using the electroplating process or the vapor deposition process. However, in a commercial application where a low cost flip chip packaging is preferred, it is advantageous not to form bumps after the chip is fabricated as in the Au stud bump method, but to form bumps in batch in its preceding stage of the wafer.
This wafer batch processing method described above clearly indicates a trend of technology in the future in consideration of a recent advancement of large scaled wafers (from 150 mmφ to 200 mmφ and to 300 mmφ), and an increasing number of chip connection pins in LSIs (large scaled integrated-circuits).
Recently, as a further challenge to an improved high-density packaging technology, a three dimensional packaging technology typically represented by a stack packaging or a lamination packaging are being discussed in many related companies.
FIGS. 10A-10C show examples of three-dimensional packaging, in which FIG. 10A shows a stacked packaging based on a wire bonding method wherein each of two semiconductor chips 56 stacked and bonded via an epoxy resin 55 is electrically connected to a circuit board 57 with a wire 54.
Further, FIG. 10B shows another packaging method that combines the flip chip method and the wire bonding method, wherein an upper semiconductor chip 56 and a lower semiconductor chip 56 are physically and electrically coupled via a bump electrode 59 and an under fill material 58 which is sealed in the periphery of the bump electrode 59. Still further, the under semiconductor chip 56 and a circuit board 57 are electrically connected with a wire 54.
Furthermore, FIG. 10C shows still another stacked structure, wherein each semiconductor chip 56 is coupled to an interposer 60 via an under fill material 58 and a bump electrode 59, and wherein a plurality of the interposers 60 and a plurality of solder balls 69 are stacked one by one on a circuit board 57, and respective interposers 60 are electrically connected with each other and to the circuit board 57 via solder balls 69.
Although FIG. 10C is a diagram showing an example of stacked packaging of semiconductor LSIs via a plurality of interposers 60, there is a problem that as the number of stacked semiconductor LSIs increases, a height of a stacked package increases. As a result, because a demand for a thinner packaging thereof becomes greater, a thinner design of LSI chips becomes more important.
Normally, a typical semiconductor LSI has a thickness of 600 μm to 700 μm in a wafer level, then a circuit thereof is formed by the processes of patterning, oxidization, impurity impregnation, wiring processing and the like, and after grinding the wafer into a thickness of approximately 400 μm, it is diced into each chip.
For example, in a stacked packaging which stacks LSI chips each having a thickness of 400 μm into four stages of lamination, a total thickness thereof will become approximately 2 mm. Now, research and developments for reducing a thickness of LSI chips as thin as 200 μm, 100 μm or even 50 μm are in progress. Still further, an extra high density stacked packaging technology using a thinner type LSI chip is advancing, which features a packaging efficiency in excess of 100% and a low package height.
By way of example, in order to obtain a thinner LSI chip, it is a normal practice to grind the chip in a state of a wafer to reduce the thickness thereof, and then dice into each chip. This method will be described with reference to FIGS. 11A-11E in the following.
FIG. 11A shows an LSI wafer 61 with its device surface 62 facing upward, which has normally a thickness of 600 μm to 700 μm. FIG. 11B shows the LSI wafer 61 having a protection sheet 63 pasted on its device surface 62. FIG. 11C shows the LSI wafer 61 which was ground and polished on its bottom surface 68 in order to reduce its thickness. After grinding and polishing to reduce the thickness, the LSI wafer 61 is subjected to a cleaning process, however, at this time, a delicate handling and care must be taken (when peeling off the protection sheet 63 or handling of the LSI wafer 61) lest a very thin LSI wafer 61 should be broken.
Next, in FIG. 11D, the protection sheet 63 is peeled off from the LSI wafer 61, and a dicing sheet 64 is pasted on a bottom surface 68 thereof. Further, FIG. 11E shows a step of fabricating LSI chips 65 through a dicing process by dicing the LSI wafer 61 into respective chips. By way of example, there is a problem that a crack tends to occur easily when the thickness of the LSI chip 65 which was ground becomes thinner at the time of dicing of the LSI wafer 61.
On the other hand, recently, a new technology called as “DBG (dicing before grinding)” is introduced and drawing attention as a new grinding method which minimizes cracks of LSI chip 65 and is capable of reducing the thickness thereof.
FIGS. 12A-12E show the so-called “DBG (dicing before grinding)” method. FIG. 12A shows the LSI wafer 61 with its device surface 62 facing upward. FIG. 12B shows an LSI wafer 61 having a dicing sheet 64 pasted on its bottom surface 68. In FIG. 12C, the LSI wafer 61 having a thickness of 600 μm, for example, is subjected to a half-dicing to cut into a depth of, for example, 200 μm from a device surface 62 with a blade 66 or the like.
In FIG. 12D, the dicing sheet 64 is removed from the bottom surface 68 of the LSI wafer 61, and a re-pasting protection sheet 67 is pasted on the device surface 62 which was applied the half-dicing. Then, in FIG. 12E, grinding and polishing of the LSI wafer 61 is applied from the bottom surface 68 thereof to fabricate the LSI wafer 61 into respective chips. As a result, a very thin LSI chip 65 having a thickness of 100 μm or less and a minimum chip crack is easily obtained according to the present invention.
Now, the above-mentioned CSP (chip scale package) which is an approach to a high density packaging of LSIs by minimizing sizes of respective chips thereof is comprised of several common circuit blocks as viewed from the standpoint of a digital device circuit block diagram, and there is also emerging such a process to provide these common circuit blocks in a multi package or in a MCM (multi chip module). Provision of SRAM (static RAM), flash memory and a microcomputer in one chip package in a digital portable telephone is one example thereof.
This MCM technology is expected to attain a significant advantage also in a one-chip system LSI of a recent development. Namely, when integrating a group of memory, logic and analog LSIs on one chip, different LSI fabrication processes must be handled in a same wafer processing stage, thereby substantially increasing the number of masks and processing steps, with its TAT (turnaround time) for development being prolonged. Also, a low yield in production resulting from the increased steps of processing is a serious problem which cannot be ignored. For this reason, it is considered to be promising to fabricate respective LSIs individually, and then package them in an MCM.
FIG. 9 indicates a semiconductor wafer 61 fabricated by a conventional wafer batch processing. Despite a high yield of production is required for the leading-edge LSIs, the number of defective chips 29 partitioned by a scribe line 70 and marked with “×” is actually greater than the number of non-defective chips 30 marked with “◯”.
On the other hand, the wafer batch solder bump forming process is advantageous in terms of packaging because it can be applied to the provision of an area pad, and enables a batch reflow or a double side mounting. However, it has a disadvantage when being applied to the processing of a leading-edge wafer 61 which normally has a low yield of production, and because a cost of production per non-defective chip 30 will substantially increase.
Further, there has been such a problem that if bare chips are purchased from the other manufacturers or venders, it is extremely difficult to form bumps on them due to a varied design specification. Namely, although the above-mentioned two types of bump forming methods have their own merits, they cannot be used in all fields. Therefore, the above-mentioned wafer batch bump forming method is advantageous for use in such a case where the number of terminals accommodated within a single wafer is large (for example, 50000 terminals/wafer), or for forming low damage bumps applicable to the area pad.
Further, when the semiconductor wafer 61 indicated in FIG. 9 is diced along the scribe line 70, a damage such as a stress or a crack occurs in the chip due to its dicing, which may lead to a failure. Furthermore, if a process of forming solder bumps in batch on the semiconductor wafer 61 which includes both the conforming chips 30 and the defective chips 29 is allowed to proceed, the process applied to the defective chips 29 is wasted, thereby increasing the cost of manufacture.
In Japanese Patent Application Publication Laid-Open Number 9-260581, a method of forming a wiring layer for interconnection between devices is disclosed wherein a plurality of semiconductor chips are firmly bonded on a silicon wafer, embedded into a resin formed on a substrate made of alumina or the like under pressure, then peeled off so as to provide a flat wafer surface and form the wiring layer for interconnection between the devices on this flat wafer surface by photolithography.
According to this conventional method, although it is proposed that a wafer batch processing becomes possible and a low cost manufacture thereof by a merit of mass production is attained, however, because there exists a hard substrate made of alumina under the bottom surfaces of these semiconductor chips which are arrayed on the wafer, at the time of scribing and cutting into each dice, the hard substrate present under the bottom surfaces of the chips must be cut together with the resin between adjacent chips, thereby likely to damage a cutter blade. In addition, although the side walls of the chip are covered with the resin, there exists only the hard substrate on the bottom surface thereof, therefore, there are such problems that the bottom surface of the chip is not protected effectively and adhesion therebetween is weak.
Further, a conventional grinding process for grinding the bottom surface of the wafer causes a grinding damage such as stress, crack and the like to arise after its mechanical processing. Because this mechanical damage leads to an occurrence of chip cracks when mounting a very thin chip on a printed board and in its handling, a process of removal of a damaged layer by polishing or chemical etching becomes necessary after the mechanical grinding.
Further, in the “DBG (dicing before grinding)” process of FIGS. 12A-12E, a chemical etching is applied after grinding the LSI wafer from its bottom surface, at this time, a chemical etching solution circulates to the device surface of the chip. Therefore, if adhesion between a double-sided adhesion sheet and the device surface of the chip 4 is weak, there occurs a serious problem that the device surface is easily etched.
The present invention is contemplated to solve the above-mentioned problems associated with the conventional art, and to provide a chip-like electronic component such as an LSI chip which may be comprised of a leading-edge LSI or a bare chip purchased from the other manufacturer, and can be mass-produced at a high yield, low cost and high reliability.
In addition, it is another object of the invention to provide a method of manufacturing the chip-like electronic components such as thin type LSI chips or the like which can minimize the damages resulting from grinding of the bottom surface of the LSI chip.
The present invention is directed to a chip-like electronic component such as a semiconductor chip having at least electrodes formed solely on one surface thereof, its side wall covered with a protective material, and its bottom surface opposite to the above-mentioned one surface is fabricated to reduce its thickness, and also the invention is directed to a pseudo wafer having a plurality of a same and/or different types of the above-mentioned chip-like electronic components which are bonded spaced apart from each other by the protective material, and the bottom surfaces opposite to their electrode surfaces are fabricated to reduce its thickness.
According to another aspect of the present invention, a method of manufacturing the pseudo wafer is provided, which is comprised of the steps of: pasting an adhesive material on a substrate, which retains an adhesive strength prior to its processing and loses the adhesive strength after its processing; fixing a plurality of a same and/or different types of semiconductor chips on this adhesive material with their surfaces having electrodes facing downward; coating a protective material on a whole area of the surfaces of the plurality of the same and/or the different types of semiconductor chips including interspatial gaps therebetween; removing the above-mentioned protective material from the bottom surface thereof opposite to the electrode surface to the bottom surface of the semiconductor chip; applying a predetermined processing to the adhesive material so as to lower the adhesive strength thereof; and peeling off a pseudo wafer having these semiconductor chips bonded thereon. In addition, a method of manufacturing a chip-like electronic component is provided, which is comprised of the step of cutting off the protective material between respective semiconductor chips on the wafer so as to divide into respective discrete semiconductor chips or chip-like electronic components.
According to the present invention, because the side surfaces of the chip-like electronic component such as the semiconductor chip or the like (hereinafter explained by referring to the semiconductor chip such as LSI chip) other than its electrode surface are protected with a protective material, the chip is ensured to be protected in its post chip handling using such as a collet, thereby facilitating its handling and enabling an excellent package reliability to be obtained. In addition, because the bottom surface of the electronic component (opposite to the electrode surface) is fabricated to reduce its thickness, an improved stack (lamination) packaging density due to a thinner structure is attained advantageously.
Further, by the method comprising the steps of: pasting on a substrate solely non-defective chips which are diced and selected from a semiconductor wafer; coating them wholly with the protective material, though a part of them is removed by grinding afterward; then peeling the wafer bonding these chips from the adhesive material, a pseudo wafer of the present invention as if comprising entirely of the non-defective chips is obtained. Therefore, a wafer batch bump treatment for these non-defective chips becomes possible, thereby allowing to form bump chips at a lower cost, and when dicing these chips from the pseudo wafer, the portion of the protective material which is easy to cut and placed between adjacent chips is cut along the scribe line thereby without causing any adverse effect (such as strain, burr, crack and the like damages) to occur on the body of these chips. In addition, because the side surfaces of these chips are coated with the protective material, an Ni electroless plating process can be executed as well. Further, not only in-house produced wafers but also bare chips purchased from the other manufacturers are allowed to be treated likewise to form the solder bump easily.
By the way, it is very rare that all of a plurality of different types of LSI chips to be packaged in an MCM are supplied from a same semiconductor manufacturer because of an increasing burden to invest on several leading edge semiconductor production lines simultaneously. Therefore, by opting not to purchase a whole bunch of chips of SRAMs, flash memories, microcomputers or even central processor units (CPUs) from the same semiconductor manufacturer, but to purchase them individually from different chip manufacturers who are most specialized in any one of these leading-edge technologies, they can be assembled in an MCM according to the present invention. In addition, the substrate described above can be used in repetition advantageously for cost reduction of bump forming and for environmental protection.
Namely, a novel process is provided according to the present invention, the same comprising the steps of: pasting a plurality (of a same type) and/or different types of LSI chips, for example, on a quartz substrate, apart from each other at a predetermined distance, with their device surfaces facing down; coating with an insulating material (such as a resin, SiOx by SOG (spin on glass)) from the bottom side of the chips, and hardening the same; reducing a total thickness by grinding or the like; and removing the pseudo wafer from the substrate, with the periphery of these chips thereon being protected by the insulating material. Thereby, this novel process of the invention enables readily to provide a method of fabricating thinner type chip components featuring a minimal damage, and an easier handling thereof.
Further, in the above-mentioned processing, the damage (such as stress, crack and the like) hardly remains even if the semiconductor chip is fabricated thinner. Further, a mechanical impact exerted on the body of the chip during packaging handling or the like is mitigated because that the sidewalls of the chip are covered with and protected by the protective material. Still further, because that respective side walls of respective chips are bonded integrally with the insulating film, there is no need of applying a chemical etching process after the grinding process as required conventionally, thereby preventing the device surface of each LSI chip from being etched by a penetrating solution.
The above-mentioned substrate made of quartz or the like can be used repeatedly, which is very advantageous in terms of cost reduction and environmental protection.